The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for equivalent device statistical modeling for representing a group of devices by a single equivalent device using a characteristic equivalent distribution for the equivalent device. A specific application of this equivalent device statistical modeling encompasses mechanisms for bitline leakage modeling.
As memory array architectures are pushed to their practical limits by increasing requirements for density and speed, accurately estimating the memory cell failure rate of a design becomes increasingly critical. Since a finite number of redundant rows and/or columns of memory cells are available to replace those containing defective cells, a number of failed memory cells above this level of redundancy will yield a defective device. The number of defective devices or the device yield is then directly related to the memory cell failure rate. Larger memory arrays being fabricated today have increasingly stringent failure rate control requirements. For example, in order to achieve a yield of 90% in a one-million memory cell array without redundancy, a failure rate below 5σ must be held.
Traditional techniques, such as Monte-Carlo analysis, produce accurate results at a cost of a large number of iterations, due to the random sampling of the entire probability space of the independent variables that are treated in the analysis. As the memory cell failure rate decreases, the number of samples and iterations required for accurate analysis becomes increasingly large, because of the relatively sparse distribution of samples in the distribution tail(s) that correspond to failed memory cells. The effect of circuit changes on memory cell read and writeability, as well as minimum read and write cycle times and margins, are difficult to estimate at very low failure rate levels. Thus, such low failure rates cause further complications for adjusting designs to achieve the best result.
Techniques other than Monte-Carlo analysis have been implemented for estimating memory cell failure rates, each with related drawbacks. Sensitivity analysis is a well-known technique in which the gradients of the various independent variables are used to determine the bounds of the non-failure confidence region. However, accurate estimates of the failure rate are not typically produced by sensitivity analysis, as sensitivity analysis by its very nature cannot determine the exact overlapping impact of all independent variables on the memory cell failure rate at once. Another technique that can accurately estimate the failure rate is the grid analysis approach, in which the grid size can be made arbitrarily small. However, the number of simulations increases exponentially with the number of independent variables and typically a large amount of custom coded program control (scripting) must be employed to direct the analysis.
In addition, this analysis of an integrated circuit design, and thus the determination of an expected memory cell failure rate, becomes increasingly more difficult when taking into account dynamic failures, such as bitline leakage failures. As described in Dilillo et al., “Leakage Read Fault in Nanoscale SRAM: Analysis, Test and Diagnosis,” International Design and Test Workshop, 19-20 Nov. 2006, most memory testing mechanisms rely on classic fault models such as stuck at fault, coupling fault, and transition fault. However, dynamic faults, such as dynamic faults due to leakage currents, are a more complex class of faults requiring complex testing mechanisms.
In SRAM structures, the leakage currents that flow through the two pass transistors of unselected cells interfere with the read operation of the SRAM. The read operation in SRAM memories relies on the detection of differential voltage levels between the bit lines generated by the selected cells. In the same column where the cell to be read is placed, leakage currents of unselected cells generate another differential effect that may be opposite to the one useful for the read function. The consequent “mask effect” is generally considered the cause of performance reduction in SRAM structures, especially in terms of operating frequency reduction. These leakage currents may further induce the sense amplifier of the SRAM structure to be unable to detect properly the correct value for the memory output with the occurrence of leakage read faults.
The modeling of such bitline leakages for purposes of analysis and determining of failure rates is very complex, involving large sets of independent variables. For example, if there is an array of 100 devices, each having voltage fluctuations, this translates to an analysis problem dealing with at least 100 independent voltage fluctuation variables. This may lead to a 100D dimensional space that needs to be sampled to accurately model and analyze the impact of bitline leakages on the failure rate of a SRAM structure. It is much easier to model a smaller dimensional space, e.g., a 3D space, and sample it based on a 3D model as opposed to modeling a 100D dimensional space and sampling it. This is true for different methodologies including grid based methods, methods that rely on response surface modeling, and any other methods that employ uniform analysis for prescreening phase (like mixture importance sampling method) to find important failure regions.